Placement Techniques for VLSI Layout Using Sequence-Pair Legalization

This thesis considers the placement problem in VLSI layout, which deals with layout optimization of integrated circuits. Most practical formulations of this problem are NP-hard. The most widely used formulations of this problem consider placement of rectangles within a rectangular container. The rectangles represent logical components and are called modules. Modules are connected by wires and a common objective is to minimize the wire-length. Most authors consider modules of equal height, the so-called standard-cells, but often practical instances of the problem also contain rectangles of varied height. Therefore there is a need for placement methods which are not limited to standardcell placement. These problems fall in two groups mixed-cell placement which is a combination of standard-cells and a limited number of larger modules of unequal height, and general-cell placement which contain modules of arbitrary sizes. The placement process is commonly broken in two parts; global and final placement. Global placement generates a good initial solution which often contains overlap. Final placement generally optimizes each module of the placement individually and generates non-overlapping legal solutions. We define the problem with different wire-length objective functions and present a survey of successful placement techniques from the last decade. We present a novel legalization technique for general-cell instances which has asymptotic running time , and is capable of removing overlap from placements which is a well-known problem for many placement heuristics. We use the legalization algorithm to create a new global placement method which combines legalization and well-known analytic methods. We present a new final placement method which is based on relaxation based neighborhood search and use the legalization algorithm to remove overlap during optimization. Experimental results are reported for the global and final placement heuristics on standardmixedand general-cell circuits. Experiments show promising results. New general-cell circuits based on common standard-cell circuits are placed with netlengths which are less than worse than their standard-cell counterparts. Also the new placement algorithm produces results comparable and in some cases better than those previously published and produced by commercial placement tools.